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january 2011 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 FAN3278 ? 30v pmos-nmos bridge driver FAN3278 30v pmos-nmos bridge driver features ? 8v to 27v optimum operating range ? drives high-side pmos and low-side nmos in motor control or buck step-down applications ? output drive-voltage magn itude limited: < 13v for v dd up to 30v ? biases each load device off with a 100k ? resistor when v dd below operating level ? low-voltage ttl input thresholds ? peak gate drives at 12v: +1.5a sink, -1.0a source ? internal resistors hold driver off when no inputs present ? 8-lead soic package ? rated from ?40c to +125c ambient applications ? motor control with pmos / nmos half-bridge configuration ? buck converters with high-side pmos device; 100% duty cycle operation possible ? logic-controlled load circuits with high-side pmos switch description the FAN3278 dual 1.5a gate driver is optimized to drive a high-side p-channel mosfet and a low-side n-channel mosfet in mo tor control applications operating from a voltage rail up to 27v. internal circuitry limits the voltage applied to the gates of the external mosfets to 13v maximum. the driver has ttl input thresholds and provides buffer and level translation from logic inputs. internal circuitry prevents the output switching devices from operating if the v dd supply voltage is below the ic operation level. internal 100k ? resistors bias the non-in verting output low and the inverting output to v dd to keep the external mosfets off during startup intervals when logic control signals may not be present. the FAN3278 driver incorporates mosfet devices for the final output stage, provid ing high current throughout the mosfet turn-on / turn-o ff transition to minimize switching loss. the internal gate-drive regulators provide optimum gate-driv e voltage when operating from a rail of 8v to 27v. the FAN3278 can be driven from a voltage rail of less than 8v; however, its gate drive current is reduced. the FAN3278 has two independent enable pins that default to on if not connec ted. if the enable pin for non-inverting channel a is pulled low, outa is forced low. if the enable pin for inverting channel b is pulled low, outb is forced high. if an input is left unconnected, internal resistors bias the inputs such that the external mosfets are off. figure 1. typical application
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 2 FAN3278 ? 30v pmos-n mos bridge driver ordering information part number logic input threshold packing method FAN3278tmx non-inverting channel and inverting channel with dual enable ttl 2,500 units on tape & reel figure 2. typical 3-phase blower motor drive application
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 3 FAN3278 ? 30v pmos-n mos bridge driver pin configuration figure 3. pin configuration (top view) thermal characteristics (1) package ? jl (2) ? jt (3) ? ja (4) ? jb (5) ? jt (6) unit 8-pin small-outline integrated circuit (soic) 40 31 89 43 3 c/w notes: 1. estimates derived from thermal simulation ; actual values depend on the application. 2. theta_jl ( ? jl ): thermal resistance between the semiconductor j unction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a pcb. 3. theta_jt ( ? jt ): thermal resistance between the semiconductor junction and the top su rface of the package, assuming it is held at a uniform te mperature by a top-side heatsink. 4. theta_ja ( ja ): thermal resistance between junction and ambi ent, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convection wi th no heatsink using a 2s2p board, as specified in jedec standards jesd51-2, jesd51- 5, and jesd51-7, as appropriate. 5. psi_jb ( ? jb ): thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference poin t for the thermal environment defined in note 4. for the soic-8 package, the board reference is def ined as the pcb copper adjacent to pin 6. 6. psi_jt ( ? jt ): thermal characterization parameter providin g correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in note 4. pin definitions pin# name description 1 ena enable input for channel a . pull pin low to inhibit driver a. ena has ttl thresholds. 8 enb enable input for channel b . pull pin low to inhibit driver b. enb has ttl thresholds. 3 gnd ground . common ground reference for input and output circuits. 2 ina input to channel a . 4 inb input to channel b . 7 outa gate drive output a : held low unless required input is present and v dd is above the internal voltage threshold where the ic is functional. 5 outb gate drive output b (inverted from the input). held high unless the required input is present and v dd is above the internal voltage threshold where the ic is functional. 6 vdd supply voltage . provides power to the ic.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 4 FAN3278 ? 30v pmos-n mos bridge driver output logic FAN3278 (channel a) FAN3278 (channel b) ena ina outa enb inb outb 0 0 (7) 0 0 0 (7) 1 0 1 0 0 1 1 1 (7) 0 (7) 0 1 (7) 0 (7) 1 1 (7) 1 1 1 (7) 1 0 note: 7. default input signal if no external connection is made. block diagram 6 vdd 7 5 ina 2 100k ena 1 gnd 3 v dd 100k 8 v dd enb inb 4 outa 100k 100k 100k 100k outb low-side drive regulator high-side drive regulator 13v v dd -13v hs predriver ls predriver figure 4. block diagram
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 5 FAN3278 ? 30v pmos-n mos bridge driver absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to pgnd -0.3 30.0 v v en ena, enb to gnd gnd - 0.3 v dd + 0.3 v v in ina, inb to gnd gnd - 0.3 v dd + 0.3 v v out outa, outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature -55 +150 oc t stg storage temperature -65 +150 oc esd electrostatic discharge protection level human body model, jedec jesd22-a114 2 kv charged device model, jedec jesd22-c101 2 recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 8 27 v v en enable voltage (ena, enb) 0 v dd v v in input voltage (ina, inb) 0 v dd v t a operating ambient tem perature -40 +125 c
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 6 FAN3278 ? 30v pmos-n mos bridge driver electrical characteristics unless otherwise noted, v dd =12v and t j =-40c to +125c. currents are defined as positive into the device (i sink ) and negative out of the device (i source ). symbol parameter conditions min. typ. max. unit supply v dd optimum operating range (8) 8 27 v i dd supply current inputs / en not connected 1.3 2.0 ma v on turn-on voltage (9) ina=ena=v dd , inb=enb=0v 3.8 v v hys turn-on / turn-off hysteresis (9) ina=ena=v dd , inb=enb=0v 10 mv input (9) v il inx logic low threshold 0.8 1.1 v v ih inx logic high threshold 1.80 2.25 v v hys logic hysteresis voltage 0.4 0.7 1.0 v enable v enl enable logic low threshold en from 5v to 0v 0.8 1.2 v v enh enable logic high threshold en from 0v to 5v 1.60 2.25 v v hys logic hysteresis voltage (10) 0.7 v r pu enable pull-up resistance 100 k ? t d1 propagation a delay, en rising (11) 0 - 5v in , 1v/ns slew rate 44 70 ns t d2 propagation a delay, en falling (11) 0 ? 5v in , 1v/ns slew rate 33 60 ns t d2 propagation b delay, en rising (11) 0 - 5v in , 1v/ns slew rate 39 70 ns t d1 propagation b delay, en falling (11) 0 ? 5v in , 1v/ns slew rate 29 60 ns continued on the following page? timing diagrams figure 5. non-inverting figure 6. inverting 90% 10% output input or enable t d1 t d2 t rise t fall v inl v inh
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 7 FAN3278 ? 30v pmos-n mos bridge driver electrical characteristics (continued) unless otherwise noted, v dd =12v and t j =-40c to +125c. currents are defined as positive into the device (i sink ) and negative out of the device (i source ). symbol parameter conditions min. typ. max. unit output i pk_off out current, peak, turn-off (10) c load =0.1f, f=1khz 1.5 a i pk_on out current, peak, turn-on (10) c load =0.1f, f=1khz -1.0 a i off out current, mid-voltage, turn-off (10 out at v dd , c load =0.1f, f=1khz 1.0 a i on out current, mid-voltage, turn-on (10) out at v dd /2, c load =0.1f, f=1khz -0.5 a v outa outa drive voltage v dd =27v, ina=?hi? 11 13 v v outb outb drive voltage, v dd ? v outb v dd =27v, ina=?hi? 11 13 v v outa outa drive voltage v dd =10v, inb=?hi? 6.5 7.0 v v outb outb drive voltage, v dd ? v outb v dd =10v, inb=?hi? 6.5 7.0 v r o_a_sink outa sink impedance (turn-off) (10) v dd =6v, c load =0.1f 4.2 ? r o_a_src outa source impedance (turn-on) (10) v dd =6v, c load =0.1f 10.3 ? r o_b_sink outb sink impedance (turn-on) (10) v dd =6v, c load =0.1f 6.8 ? r o_b_src outb source impedance (turn-off) (10) v dd =6v, c load =0.1f 13.7 ? t on,n output a rise time (11) c load =1000pf to gnd 17 30 ns t off,n output a fall time (11) c load =1000pf to gnd 8 15 ns t on,p output b fall time (11) c load =1000pf to v dd 21 30 ns t off,p output b rise time (11) c load =1000pf to v dd 8 15 ns t d1 output propagation delay on (11) 0 - 5v in , 1v/ns slew rate 45 70 ns t d2 output propagation delay off (11) 0 - 5v in , 1v/ns slew rate 35 60 ns i rvs output reverse current withstand (10) 500 ma notes: 8. the internal gate-drive regulators provide optimum gate-drive voltage when operating from a rail of 8v to 27v. the FAN3278 can be driven from a voltage rail of less than 8v; however, with reduced gate drive current. 9. en inputs have near-ttl thresholds (refer to the enable section) . 10. not tested in production. 11. see the timing diagrams of figure 5 and figure 6.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 8 FAN3278 ? 30v pmos-n mos bridge driver typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 7. i dd (static) vs. supply voltage (12) figure 8. i dd (static) vs. temperature (12) figure 9. i dd (no load) vs. frequency figure 10. i dd (1nf load) vs. frequency figure 11. input thresholds vs. temperature
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 9 FAN3278 ? 30v pmos-n mos bridge driver typical performance characteristics typical characteristics are provided at t a =25c and v dd =12v unless otherwise noted. figure 12. propagation delays vs. temperature figure 13. propagation delays vs. temperature figure 14. rise and fall times vs. temperature figure 15. rise and fall times vs. temperature figure 16. gate drive voltage vs. temperature figure 17. gate drive voltage vs. temperature note: 12. for any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high; static i dd increases by the current flowing through the corresponding pull-up/down resistor, shown in figure 4.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 10 FAN3278 ? 30v pmos-n mos bridge driver applications information input thresholds the FAN3278 driver has ttl input thresholds and provides buffer and level translation functions from logic inputs. the input thresholds meet industry- standard ttl-logic thresholds, independent of the v dd voltage, and there is a hysteresis voltage of approximately 0.4v. these le vels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6v/s or faster, so a rise time from 0 to 3.3v should be 550ns or less. with reduced slew rate, circuit noise could cause the driver input voltage to exc eed the hysteresis voltage and retrigger the driver input inadvertently. static supply current in the i dd (static) typical performance characteristics (see figure 7 and figure 8) , the curve is produced with all inputs / enables floating (outa is low, outb is high) and indicates the lowest static i dd current for the tested configuration. for ot her states, additional current flows through the 100k ? resistors on the inputs and outputs, shown in the block diagram (see figure 4) . in these cases, the static i dd current is the value obtained from the curves plus this additional current. gate drive regulator FAN3278 incorporates internal regulators to regulate the gate drive voltage. the out put pin slew rate is determined by this gate drive voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time is needed at the mosfet gate. startup operation the FAN3278 startup logic is optimized to drive a ground- referenced n-channel mosfet with channel a and a v dd -referenced p-channel mosfet with channel b. the optimum operating voltag e of the FAN3278 is 8v to 27v. it has an internal ?watchdog? circuit that provides a loose uvlo turn-on voltage (v on ) of approximately 3.8v with a small hysteresis of about 10mv. however, it is recommended that v dd is greater than 4.75v in all application circuits. when the v dd supply voltage is below the level needed to operate the internal circuitry, the outputs are biased to hold the external mosfets in off state. internal 100k ? resistors bias the non-inverting output low and the inverting output to v dd to keep the external mosfets off during startup intervals when input control signals may not be present. figure 18 shows startup waveforms for non-inverting channel a. at power-up, the driver output for channel a remains low until v dd reaches the voltage where the device starts operating, then outa operates in-phase with ina. figure 18. non-inverting startup waveforms figure 19 illustrates startup waveforms for inverting channel b. at power-up, the driver output for channel b is tied to v dd through an internal 100k ? resistor until v dd reaches the voltage where the device starts operating, then outb operates out of phase with inb. figure 19. inverting startup waveforms it is possible, during startup, before v dd has reached approximately 4.5v, that t he output pulse width may take a few switching cycles to reach the full duty-cycle of the input pulse. this is due to internal propagation delays affecting the operation with higher switching frequency (e.g. >100khz) and slow v dd ramp-up (e.g. <20v/ms). for this reason, it is recommended that v dd should be greater than 4.75v before any ina or inb signals are present. for high-frequency applications (several hundred khz up to 1mhz), where the above recommendation of v dd > 4.75v is not possible, the use of enables to actively hold the outputs low until v dd > 4.75v assures the driver output pul se width follows the input from 4.75v up to 28v.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 11 FAN3278 ? 30v pmos-n mos bridge driver v dd bypass capacitor guidelines to enable this ic to turn a device on quickly, a local high-frequency bypass capacitor, c byp , with low esr and esl should be connected between the vdd and gnd pins with minimal trace length. this capacitor is in addition to bulk electrolytic ca pacitance of 10f to 47f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd supply to 5%. this is often achieved with a value 20 times the equivalent load capacitance c eqv , defined as q gate /v dd . ceramic capacitors of 0.1f to 1f or larger are common choices, as are dielectrics, such as x5r and x7r, with stable temperature characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased to 50-100 times the c eqv or c byp may be split into two capacitors. one should be a larger value, based on equivalent lo ad capacitance, and the other a smaller value, such as 1-10nf, mounted closest to the vdd and gnd pins to carry the higher-frequency components of the current pul ses. the bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the c byp can be twice as large as when a single channel is switching. layout and connection guidelines the FAN3278 gate driver in corporates fast-reacting input circuits, short propagat ion delays, and powerful output stages capable of deliv ering current peaks over 1.5a to facilitate fast voltage transition times. the following layout and connection guidelines are strongly recommended: ? keep high-current output and power ground paths separate from logic and enable input signals and signal ground paths. this is especially critical when dealing with ttl-level logic thresholds at driver inputs and enable pins. ? keep the driver as close to the load as possible to minimize the length of high-current traces. this reduces the series inductance to improve high- speed switching, while minimizing the loop area that can couple emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, the internal 100k ? resistors indicated on block diagrams command a low output on channel a and a high output on channel b. in noisy environments, it may be necessary to tie inputs of an unused channel to vdd or gnd using short traces to prevent noise from causing spurious output switching. ? many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output mis- triggering. these effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. for best results, make connections to all pins as short and direct as possible. ? the turn-on and turn-off current paths should be minimized, as discussed above. thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipate significant amounts of power. it is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure the part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of two components, p gate and p dynamic : p total =p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gat e current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the po wer dissipation that results from driving a mosfet with a specified gate-source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate =q g ? v gs ? f sw (2) this needs to be calculated for each p-channel and n- channel mosfet where the q g is likely to be different. dynamic pre-drive / shoot-through current: power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the ?i dd (no- load) vs. frequency? graphs in figure 9 to determine the current i dynamic drawn from v dd under actual operating conditions. p dynamic =i dynamic ? v dd (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming ? jb was determined for a similar thermal design (heat sinking and air flow): t j =p total ? ? jb + t b (4) where: t j =driver junction temperature ? jb =(psi) thermal characteri zation parameter relating temperature rise to total power dissipation t b =board temperature in location defined in note 1 under thermal resistance table. as an example of a power dissipation calculation, consider an application driving two mosfets (one p- channel and one n-channel, both with a gate charge of 60nc each) with v gs =v dd =12v. at a switching frequency of 200khz, the total power dissipation is: p gate =60nc ? 12v ? 200khz ? 2=0.288w (5) p dynamic =1.65ma ? 12v =0.020w (6) p total =0.308w (7)
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 12 FAN3278 ? 30v pmos-n mos bridge driver the soic-8 package has a junction-to-board thermal characterization parameter of ? jb =43c/w. in a system application, the localized te mperature around the device is a function of the layout and construction of the pcb along with airflow across the surfaces. to ensure reliable operation, the maximum junction temperature of the device must not exceed the absolute maximum rating of 150c; with 80% derating, t j would be limited to 120c. rearranging equation 4 determines the board temperature required to maintain the junction temperature below 120c: t b =t j - p total ? ? jb (8) t b =120c ? 0.308w ? 43c/w=107c (9) test circuit figure 20. quasi-static i out / v out test circuit differences between f an3278 and fan3268 FAN3278 and fan3268 are pin-compatible to each othe r and are designed to drive one p-channel and one n-channel mosfet in applications such as battery-powered compact fan / pump dc motor drives. however, there are key differences, highlighted in table 1. table 1. differences between FAN3278 and fan3268 FAN3278 fan3268 supply voltage 27v operating maximum 30v absolute maximum 18v operating maximum 20v absolute maximum gate drive regulator yes, since the maximum operating v dd can be as high as 27v, the gate voltage to the external mosfets is limited to about 13v. no gate drive regulator is needed. the gate drive voltage is v dd and the fan3268 switches rail-to-rail. minimum operating voltage the optimum operating range is 8v to 27v. after the ic turns on at about 3.8v, the output tracks v dd up to the regulated voltage rail of about 11~13v. below 8v of v dd , the FAN3278 operates, but (a) slower and (b) with limited gate drive voltage until it reaches around 8v. 4.1v is the uvlo turn-off voltage which is the minimum operating voltage. startup the ic starts operati ng approximately at 3.8v which acts as a loose uvlo threshold. it incorporates a ?smart startup? feature where the out puts are held off before the ic starts operating. has the tight uvlo threshold of 4.5v on / 4.1v off. incorporates ?smart startup? (outputs hel d off before ic is fully operational at the uvlo threshold). output gate drive architecture standard mos-based output structure with gate drive clamp. compound millerdrive? architecture in the final output stage to provide a more efficient gate drive current during the miller plateau stage of the turn- on/turn-off switching transition. outb gate drive current strength optimized for p-channel: the turn-off (1.5 a) is stronger than turn-on (1.0a). p-channel turn-on (2.4a) is stronger than turn-off (1.6a).
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 13 FAN3278 ? 30v pmos-n mos bridge driver table 2. related products part number type gate drive (13) (sink / src) input threshold logic package fan3111c single 1a +1.1a / -0.9a cmos single c hannel of dual-input/single-output sot23-5, mlp6 fan3111e single 1a +1.1a / -0.9a external (14) single non-inverting channel with external reference sot23-5, mlp6 fan3100c single 2a +2.5a / -1.8a cmos single channel of two-input/one-output sot23-5, mlp6 fan3100t single 2a +2.5a / -1.8a ttl single channel of two-input/one-output sot23-5, mlp6 fan3226c dual 2a +2.4a / -1.6a cmos dual inverting channels + dual enable soic8, mlp8 fan3226t dual 2a +2.4a / -1.6a ttl dual in verting channels + dual enable soic8, mlp8 fan3227c dual 2a +2.4a / -1.6a cmos dual n on-inverting channels + dual enable soic8, mlp8 fan3227t dual 2a +2.4a / -1.6a ttl dual non- inverting channels + dual enable soic8, mlp8 fan3228c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3228t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.1 soic8, mlp8 fan3229c dual 2a +2.4a / -1.6a cmos dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3229t dual 2a +2.4a / -1.6a ttl dual channels of two-input/one-output, pin config.2 soic8, mlp8 fan3268t dual 2a +2.4a / -1.6a ttl non-inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 FAN3278t dual 2a +1.4a / -1.0a ttl 30v non-inverting (nmos) and inverting (pmos) + dual enable soic8 fan3223c dual 4a +4.3a / -2.8a cmos dual inverting channels + dual enable soic8, mlp8 fan3223t dual 4a +4.3a / -2.8a ttl dual in verting channels + dual enable soic8, mlp8 fan3224c dual 4a +4.3a / -2.8a cmos dual n on-inverting channels + dual enable soic8, mlp8 fan3224t dual 4a +4.3a / -2.8a ttl dual non- inverting channels + dual enable soic8, mlp8 fan3225c dual 4a +4.3a / -2.8a cmos dual channels of two-input/one-output soic8, mlp8 fan3225t dual 4a +4.3a / -2.8a ttl dual channels of two-input/one-output soic8, mlp8 fan3121c single 9a +9.7a / -7.1a cmos singl e inverting channel + enable soic8, mlp8 fan3121t single 9a +9.7a / -7.1a ttl singl e inverting channel + enable soic8, mlp8 fan3122t single 9a +9.7a / -7.1a cmos single non-inverting channel + enable soic8, mlp8 fan3122c single 9a +9.7a / -7.1a ttl single non-inverting channel + enable soic8, mlp8 notes: 13. typical currents with out at 6v and v dd =12v. 14. thresholds proportional to an externally supplied reference voltage.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 14 FAN3278 ? 30v pmos-n mos bridge driver physical dimensions figure 21. 8-lead, small-outline integrated circuit (soic) package drawings are provided as a service to customers considering fairchild comp onents. drawings may change in any manner without notice. please note the revision and/or date on the drawin g and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package s pecifications do not expand the terms of fa irchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes: unless otherwise specified a) this packag e conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FAN3278 ? rev. 1.0.0 15 FAN3278 ? 30v pmos-n mos bridge driver

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